Field of the Invention
The present invention relates to an information processing apparatus having a programmable logic device, a method for controlling the information processing apparatus, and a storage medium.
Description of the Related Art
As a Field-Programmable Gate Array (FPGA) configuration method, a certain technique performs a configuration by using a central processing unit (CPU) as a master device. Hereinafter, this method is referred to as a “CPU master configuration”. Generally, in the CPU master configuration, a configuration is performed in two steps (refer to Japanese Patent Application Laid-Open No. 2013-098823).
The configuration in the first step (hereinafter referred to as a “first configuration”) is performed when power is supplied to an FPGA, and circuit configuration data (hereinafter referred to as “first configuration data”) is loaded into the FPGA from a read only memory (ROM) connected to the FPGA. The first configuration is performed without CPU's intervention. The first configuration data includes hardware intellectual property (IP) circuit and input/output (I/O) circuit data.
The configuration in the second step (hereinafter referred to as a “second configuration”) is performed by the CPU at an arbitrary timing after completion of the first configuration. Circuit configuration data (hereinafter referred to as “second configuration data”) is loaded into the FPGA from a hard disk drive (HDD) connected to the CPU. The second configuration data includes user logic circuit configuration data.
The CPU master configuration is mainly characterized in that the second configuration data is easily installed to an apparatus concerned. As described above, the second configuration data is stored in a secondary storage device (an HDD, a solid state drive (SSD), etc.) accessible from the CPU, and therefore can be installed from a removable medium or a network server at an arbitrary timing. The term installation means storing data in secondary storage devices from the outside, and does not include configuration operations.
Meanwhile, when handling the CPU master configuration, it is necessary to note consistency between the first and the second configuration data. The term “consistency” means combining the first and the second configuration data to achieve a normally operable FPGA circuit.
Conventionally, to check the consistency between the first and the second configuration data, there was no choice but to perform the CPU master configuration and check whether the FPGA normally operates. Therefore, the second configuration data that is inconsistent with the first configuration data may be installed, and in this case the FPGA does not normally operate. This caused complexity in installation works and malfunctions of the apparatus.